70. Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?
|Subject Name : Electronics Engineering|
|Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT|
|Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant|
|Electronics & Communication Engineering Books
|GATE 2023 Total Info||ENGG DIPLOMA||UGC NET Total Info|
|IES 2023 Total Info||PSUs 2022 Total Info||CSIR UGC NET Total Info|
|JAM 2023 Total Info||M TECH 2023 Total Info||RAILWAY 2022 Total Info|