46. A GAL is essentially a ________.
(a) non-reprogrammable PAL
(b) PAL that is programmed only by the manufacturer
(c) very large PAL
(d) reprogrammable PAL
47. GAL is an acronym for ________.
(a) Generic Array Logic
(b) General Array Logic
(c) Giant Array Logic
(d) Generic Analysis Logic
48. A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP.
(a) GAL
(b) CPLD
(c) PAL
(d) SPLD
49. The Boolean expression (A + B)(C + D) is an example of ________.
(a) LAB
(b) LUT
(c) SOP
(d) POS
50. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________.
(a) bed-of-nails
(b) boundary scan
(c) CLB
(d) CPLD
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