31. A(n) ________ is a section of embedded logic that is commonly found in FPGAs.
(a) LUT
(b) core
(c) DSP
(d) PI
32. Which of the following testing procedures has one or more external moving parts?
(a) Bed-of-nails
(b) Flying probe
(c) EXTEST
(d) Boundary scan
33. Which of the following testing procedures uses the JTAG IEEE standard?
(a) Bed-of-nails
(b) Flying probe
(c) EXTEST
(d) Boundary scan
34. The final step in the device programming sequence is ________.
(a) compiling
(b) downloading
(c) simulation
(d) synthesis
35. An SPLD listed as 16H8 would have ________.
(a) active-HIGH outputs
(b) active-LOW outputs
(c) variable-level outputs
(d) latches at the outputs
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