Linear Digital ICs » Exercise – 2
51. The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is ________.
(a) 0.0195 mV
(b) 0.195 mV
(c) 1.95 mV
(d) 19.5 mV
52. A phase-locked loop (PLL) is an electronic circuit that consists of ________.
(a) a phase detector
(b) a low-pass filter
(c) a voltage-controlled oscillator
(d) All of the above
53. In the frequency-shift keyed (FSK) signal decoder, the RC ladder filter is used to ________.
(a) remove the difference frequency component
(b) remove the sum frequency component
(c) remove both the difference and the sum frequency components
(d) None of the above
54. Time periods for monostable operation of the 555 timer can range from ________ to ________, making this IC useful for a range of applications.
(a) picoseconds, nanoseconds
(b) nanoseconds, milliseconds
(c) microseconds, many seconds
(d) None of the above
55. In the operation of two 311 voltage comparators as the voltage window detector, a high output indicates that the input is ________.
(a) above the higher reference voltage
(b) below the lower reference voltage
(c) either above the higher reference voltage or below the lower reference voltage
(d) within the high and the low reference voltages
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