5555555555
51. The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is ________.
(a) 0.0195 mV
(b) 0.195 mV
(c) 1.95 mV
(d) 19.5 mV
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
5555555555 26. What is the voltage resolution of an 8-stage ladder network? (a) Vref /128 (b) Vref /256 (c) Vref /512 (d) Vref /1024- Counters » Exercise - 1 1. The purpose of introducing feedback loop in digital counter circuit is : (a) To improve distortion (b) To improve stability (c) Synchronise input and output pulses (d) to reduce the number of input pulses to reset the counter 2. The circuit shown below is a : (a) Mod-4 counter (b) Mod-5 counter (c) Mod-6 counter (d) Mod-7 counter 3. In this type of counter, the output of the last stage is connected to the D input of the first stage. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 4. A counter is a : (a) Sequential circuit (b) Combinational circuit (c) Both combinational and sequential circuit (d) None of above 5. A counter with 10 states : (a) Cascading asynchronous counter (b) Decade counter (c) Asynchronous ripple counter (d) Ripple counter 6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 7. It is a sequential circuit that cycles through a sequence of states : (a) Multiplexer (b) Demultiplexer (c) Counter…
- 555555555528. Calculate the output voltage Vo if V1 = –V2 = 300 mV. (a) 0 V (b) –6 V (c) 6 V (d) –8 V
- 555555555518. Calculate the output of the second stage op-amp if V1 = 25 mV. (a) –0.075 V (b) 0.525 V (c) 0.06 V (d) 4.2 V
- 55555555554. What is the minimum number of conversions per second of a clock rate of 1 MHz operating a 10-stage counter in an ADC? (a) 1000 (b) 976 (c) 769 (d) 697