26. What is the voltage resolution of an 8-stage ladder network?
(a) Vref /126
(b) Vref /256
(c) Vref /512
(d) Vref /1024
27. When is the counter set to zero in the dual-slope method of conversion?
(a) Prior to the charging of the capacitor of the integrator
(b) While the capacitor is being charged
(c) At the end of the charging of the capacitor
(d) During the discharging of the capacitor
28. What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter in an ADC?
(a) 1.024 s
(b) 102.3 ms
(c) 10.24 ms
(d) 1.024 ms
29. Nota
30. On which of the following does the conversion depend in ladder-network conversion?
(a) Comparator
(b) Control logic
(c) Digital counter
(d) Clock
Related Posts
555555555550. In a ladder-network conversion, the ________ circuit provides a signal to stop the counter when the staircase voltage rises above the input voltage. (a) control logic (b) comparator (c) ladder-network (d) None of the above- 5555555555 16. What is the level of the output voltage of a ladder-network conversion? (a) The analog output voltage proportional to the digital input voltage (b) The digital output voltage proportional to the linear input voltage (c) A fixed digital value Vref (d) A fixed analog value Vref
- 555555555532. What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC? (a) Staircase voltage (b) Analog input voltage (c) Both staircase and analog input voltage (d) None of the above
- 55555555559. When the input to the 311 voltage comparator is ________ value, the output is ________ if the inverting input is connected to ground. (a) any negative, low (b) any positive, low (c) any positive, high (d) None of the above
- 5555555555 42. What is (are) the level(s) of the input voltage to a ladder-network conversion? (a) 0 (b) Vref (c) 0 V or Vref (d) None of the above