5555555555
135. A positive edge-triggered flip-flop will accept inputs only when the clock ________.
(a) is LOW
(b) changes from HIGH to LOW
(c) is HIGH
(d) changes from LOW to HIGH
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
5555555555134. An edge-triggered flip-flop can change states only when ________. (a) the trigger is HIGH (b) the D input is HIGH (c) the trigger is LOW (d) the trigger input changes levels- 555555555557. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the: (a) clock is LOW (b) slave is transferring (c) flip-flop is reset (d) clock is HIGH
- 5555555555 42. An S-R NAND latch with both of its inputs LOW has an output that is _____________. (a) unpredictable (b) floating (c) HIGH (d) LOW
- 555555555542. A common-emitter amplifier has ________ voltage gain, ________ current gain, ________ power gain, and ________ input impedance. (a) high, low, high, low (b) high, high, high, low (c) high, high, high, high (d) low, low, low, high
- 555555555561. On a master-slave flip-flop, when is the master enabled? (a) when the gate is LOW (b) when the gate is HIGH (c) both of the above (d) neither of the above