41. For the field-effect transistor, the relationship between the input and the output quantities is ________.
(a) linear
(b) nonlinear
(c) 3rd degree
(d) None of the above
42. The level of VDS is typically between ________ % and ________ % of VDD.
(a) 0, 100
(b) 10, 90
(c) 25, 75
(d) None of the above
43. In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.
(a) fixed-bias
(b) self-bias
(c) voltage-divider
(d) None of the above
44. In a universal JFET bias curve, the vertical scale labeled M is used for finding the solution to the ________ configuration.
(a) fixed-bias
(b) self-bias
(c) voltage-divider
(d) None of the above
45. In p-channel FETs, the level of VGS is ________ while the level of VDS is ________.
(a) negative, negative
(b) positive, positive
(c) negative, positive
(d) positive, negative
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555555555528. In a fixed-bias configuration, the voltage level of VGS is equal to ________. (a) VS (b) VG (c) VGS(off) (d) VP- 555555555537. In a universal JFET bias curve, the horizontal axis is ________. (a) VDS (b) ID / IDSS (c) the normalized level (d) VGS
- FET » Exercise - 3 101. Nota 102. Nota 103. Nota 104. A JFET data sheet specifies VGS(off) = –10 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V. (a) 2 mA (b) 1.4 mA (c) 4.8 mA (d) 3.92 mA 105. A JFET data sheet specifies VGS(off) = –6 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V. (a) 2 mA (b) 4 mA (c) 8 mA (d) none of the above 106. The JFET is always operated with the gate-source pn junction ________ -biased. (a) forward (b) (c) (d) 107. If VD is less than expected (normal) for a self-biased JFET circuit, then it could be caused by a(n) (a) open RG. (b) open gate lead. (c) FET internally open at gate. (d) all of the above 108. In a self-biased JFET circuit, if VD = VDD then ID = ________. (a) 0 (b) cannot be determined from information above Answ (c) (d) 109. The resistance of a JFET biased in the ohmic region is controlled by (a) VD. (b) VGS. (c) VS. (d) VDS. 110. What type(s) of gate-to-source voltage(s) can a depletion MOSFET…
- 5555555555161. The level of ________ that results in the significant increase in drain current in enhancement-type MOSFETs is called threshold voltage VT. (a) VDD (b) VDS (c) VGS (d) VDG
- DC Biasing FETs » Exercise - 2 51. In an enhancement-type MOSFET, the drain current is zero for levels of VGS less than the ________ level. (a) VGS(Th) (b) VGS(off) (c) VP (d) VDD 52. The slope of the dc load line in a voltage-divider is controlled by ________. (a) R1 (b) R2 (c) RS (d) All of the above 53. In a depletion-type MOSFET, the transfer characteristic rises ________ as VGS becomes more positive. (a) less rapidly (b) more rapidly (c) the same (d) None of the above