Counters – Exercise – 3

125. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

(a) J and K inputs must both = 0
(b) J must be 0, K doesn’t matter
(c) J doesn’t matter, K must = 0
(d) J must be 0 and K must be 1

126. Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.

(a) the most significant bit (MSB)
(b) the least significant bit (LSB)
(c) the clock signal
(d) from a composite of the MSB and LSB

127. The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.

(a) 3
(b) 5
(c) 8
(d) 10

128. A D flip-flop can be made to toggle by ________.

(a) connecting to Q to D
(b) connecting to Q to D
(c) connecting D low
(d) connecting D high

129. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up.” The third and fourth stages will ________.

(a) continue to count with correct outputs
(b) continue to count but have incorrect outputs
(c) stop counting
(d) turn into molten silicon

130. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

(a) The output word decreases by 1.
(b) The output word decreases by 2.
(c) The output word increases by 1.
(d) The output word increases by 2.

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