125. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
(a) J and K inputs must both = 0
(b) J must be 0, K doesn’t matter
(c) J doesn’t matter, K must = 0
(d) J must be 0 and K must be 1
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Counters » Exercise - 1111. ________ is the modulus of the counter shown below. (a) 200 (b) 19 (c) 0.005 (d) 5000- 555555555567. Why are the S and R inputs of a gated flip-flop said to be synchronous? (a) They must occur with the gate. (b) Th (c) (d)
- Flip-Flops » Exercise - 120. The master slave JK flip-flop is effectively a combination of : (a) an SR flip-flop and a D flip-flop (b) an SR flip-flop and a T flip-flop (c) a T flip-flop and a D flip-flop (d) two T flip-flops
- Counters » Exercise - 136. The terminal count of a typical modulus-10 binary counter is ________. (a) 0000 (b) 1010 (c) 1001 (d) 1111
- Counters » Exercise - 137. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse? (a) 1101 (b) 1011 (c) 1111 (d) 0000