111. The ________ can generate any possible logic function of the input variables because it generates every possible AND product term.
(a) GAL
(b) SOP
(c) PROM
(d) LAB
112. In a programmable logic device circuit diagram, the inputs to each of the OR gates are designated by ________.
(a) a dot
(b) a bus
(c) a single line
(d) 4 inputs
113. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with ________ being the most common.
(a) SRAM
(b) flash
(c) antifuse
(d) SRAM and flash
114. ________ is a mature technology consisting of numerous subfamilies that have been developed over many years of use.
(a) TTL
(b) CMOS
(c) ECL
(d) None of the above
115. Most complex digital designs include ________.
(a) standard logic devices
(b) ASIC devices
(c) microprocessor/DSP devices
(d) a mix of different hardware categories
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51. An Altera FLEX10K device uses a(n) ________ architecture. (a) OR array (b) AND array (c) OR and AND array (d) look-up table 52. In a FLEX10K device, the carry chain provides a fast carry forward function between ________. (a) LUTs (b) EABs (c) LEs (d) LABs 53. The GAL16V8 has architecture that is very similar to the ________ device. (a) PAL (b) PROM (c) PLD (d) SPLD 54. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins. (a) 100-pin (b) 120-pin (c) 140-pin (d) 160-pin 55. Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________. (a) HCPLDs (b) full custom (c) GAL (d) FPLDs 56. The distinction between CPLDs and FPGAs is ________. (a) well known (b) very small (c) often fuzzy (d) very large 57. The ________ is the most popular standard logic device family today. (a) TTL (b) CMOS (c) ECL (d) None of the above 58. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB? (a) 0 (b) 5 (c) 10 (d)…- Home » Electronics Engineering » Digital Electronics » Logic Gates
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