106. Design costs for standard cell ASICs are ________ those for MPGAs.
(a) lower than
(b) about the same as
(c) higher than
(d) none of the above
107. Gated arrays are ________ circuits that offer hundreds of thousands of gates.
(a) VLSI
(b) full custom
(c) LSI
(d) ULSI
108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
(a) AND array
(b) Look-up table
(c) OR array
(d) AND and OR array
109. Full custom ICs can operate at ________ and require the ________.
(a) lowest speed, largest die area
(b) lowest speed, smallest die area
(c) highest speed, largest die area
(d) highest speed, smallest die area
110. The SPLD classification includes the ________ PLD devices.
(a) earliest
(b) smallest
(c) largest
(d) newest
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51. An Altera FLEX10K device uses a(n) ________ architecture. (a) OR array (b) AND array (c) OR and AND array (d) look-up table 52. In a FLEX10K device, the carry chain provides a fast carry forward function between ________. (a) LUTs (b) EABs (c) LEs (d) LABs 53. The GAL16V8 has architecture that is very similar to the ________ device. (a) PAL (b) PROM (c) PLD (d) SPLD 54. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins. (a) 100-pin (b) 120-pin (c) 140-pin (d) 160-pin 55. Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________. (a) HCPLDs (b) full custom (c) GAL (d) FPLDs 56. The distinction between CPLDs and FPGAs is ________. (a) well known (b) very small (c) often fuzzy (d) very large 57. The ________ is the most popular standard logic device family today. (a) TTL (b) CMOS (c) ECL (d) None of the above 58. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB? (a) 0 (b) 5 (c) 10 (d)…- Home » Electronics Engineering » Digital Electronics » Logic Gates
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