5555555555
41. If we use an AND gate to inhibit a signal from passing, one of the inputs must be _________.
(a) LOW
(b) HIGH
(c) inverted
(d) floating
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
555555555580. The output of an exclusive-OR gate is HIGH if ________. (a) all inputs are LOW (b) all inputs are HIGH (c) the inputs are unequal (d) none of the above- 555555555531. If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n): (a) AND (b) NAND (c) NOR (d) OR
- 555555555556. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n): (a) AND (b) NAND (c) NOR (d) OR
- 555555555542. A NAND gate has: (a) LOW inputs and a LOW output (b) HIGH inputs and a HIGH output (c) LOW inputs and a HIGH output (d) None of the these
- Logic Gates » Exercise - 114. The output of a ......... gate is only 1 when all of its inputs are 1. (a) NOR (b) XOR (c) AND (d) NOT