5555555555
144. When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.
(a) be invalid
(b) not change
(c) remain unchanged
(d) toggle
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant
Electronics & Communication Engineering Books
Related Posts 555555555531. When both inputs of a J-K flip-flop cycle, the output will: (a) be invalid (b) not change (c) change (d) toggle Tags: change, flip, flops, inputs, j-k, output, will, invalid, toggle, electronics
5555555555102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle Tags: flip, flops, j-k, inputs, clock, will, output, toggle, electronics, engineering
555555555589. A J-K flip-flop is in a "no change" condition when ________. (a) J = 1, K = 1 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 0, K = 0 Tags: flip, flops, j-k, change, electronics, engineering
5555555555148. The term hold always means ________. (a) (b) (c) (d) no change Tags: flip, flops, change, electronics, engineering
5555555555147. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are: (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0 Tags: flip, flops, output, inputs, electronics, engineering