59. Which of the following procedures could be used to check the parallel loading feature of a counter?
(a) Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs. (b) Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs. (c) Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW. (d) Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.
Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Counters » Exercise - 1119. In order to check the CLR function of a counter, ________. (a) apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state (b) ground the CLR input and check to be sure that all of the Q outputs are LOW (c) connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH (d) connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling
Counters » Exercise - 1 1. The purpose of introducing feedback loop in digital counter circuit is : (a) To improve distortion (b) To improve stability (c) Synchronise input and output pulses (d) to reduce the number of input pulses to reset the counter 2. The circuit shown below is a : (a) Mod-4 counter (b) Mod-5 counter (c) Mod-6 counter (d) Mod-7 counter 3. In this type of counter, the output of the last stage is connected to the D input of the first stage. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 4. A counter is a : (a) Sequential circuit (b) Combinational circuit (c) Both combinational and sequential circuit (d) None of above 5. A counter with 10 states : (a) Cascading asynchronous counter (b) Decade counter (c) Asynchronous ripple counter (d) Ripple counter 6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 7. It is a sequential circuit that cycles through a sequence of states : (a) Multiplexer (b) Demultiplexer (c) Counter…
Counters » Exercise - 197. What is meant by parallel load of a counter? (a) Each FF is loaded with data on a separate clock. (b) The counter is cleared. (c) (d)
Shift Registers » Exercise - 155. When is it important to use a three-state buffer? (a) when two or more outputs are connected to the same input (b) when all outputs are normally HIGH (c) when all outputs are normally LOW (d) when two or more outputs are connected to two or more inputs
Counters » Exercise - 1119. In order to check the CLR function of a counter, ________. (a) apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state (b) ground the CLR input and check to be sure that all of the Q outputs are LOW (c) connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH (d) connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling