43. What function does the CTR DIV 8 circuit given below perform?
(a) It divides the clock frequency down to match the frequency of the serial data in.
(b) The divide-by-8 counter is triggered by the control flip-flop and clock, which then allows the data output register to begin storing the input data. Once all eight data bits are stored in the data output register, the data output register and the divide-by-8 counter trigger the one-shot. The one-shot then begins the process all over again.
(c) The divide-by-8 counter is used to verify that the parity bit is attached to the input data string.
(d) It keeps track of the eight data bits, triggering the transfer of the data through the output register and the one-shot, which then resets the control flip-flop and divide-by-8 counter.
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Counters » Exercise - 161. How many data bits can be stored in the register shown below? (a) 5 (b) 32 (c) 31 (d) 4- Counters » Exercise - 1108. In order to use a shift register as a counter, ________. (a) the register's serial input is the counter input and the serial output is the counter output (b) the parallel inputs provide the input signal and the output signal is taken from the serial data output (c) serial in/serial out register must be used (d) the serial output of the register is connected back to the serial input of the register
- 555555555565. The output of a gated S-R flip-flop changes only if the: (a) flip-flop is set (b) control input data has changed (c) flip-flop is reset (d) input data has no change
- Counters » Exercise - 197. What is meant by parallel load of a counter? (a) Each FF is loaded with data on a separate clock. (b) The counter is cleared. (c) (d)
- Counters » Exercise - 192. The parallel outputs of a counter circuit represent the: (a) parallel data word (b) clock frequency (c) counter modulus (d) clock count