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134. A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________.
(a) the same as the clock
(b) twice the clock frequency
(c) one-half the clock frequency
(d) one-fourth the clock frequency
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Counters » Exercise - 1 1. The purpose of introducing feedback loop in digital counter circuit is : (a) To improve distortion (b) To improve stability (c) Synchronise input and output pulses (d) to reduce the number of input pulses to reset the counter 2. The circuit shown below is a : (a) Mod-4 counter (b) Mod-5 counter (c) Mod-6 counter (d) Mod-7 counter 3. In this type of counter, the output of the last stage is connected to the D input of the first stage. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 4. A counter is a : (a) Sequential circuit (b) Combinational circuit (c) Both combinational and sequential circuit (d) None of above 5. A counter with 10 states : (a) Cascading asynchronous counter (b) Decade counter (c) Asynchronous ripple counter (d) Ripple counter 6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 7. It is a sequential circuit that cycles through a sequence of states : (a) Multiplexer (b) Demultiplexer (c) Counter…- Counters » Exercise - 1123. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________. (a) 1.25 kHz (b) 2.50 kHz (c) 160 kHz (d) 320 kHz
- Counters » Exercise - 130. A 4-bit counter has a maximum modulus of ________. (a) 3 (b) 6 (c) 8 (d) 16
- 555555555552. Which of the following logic families has the highest maximum clock frequency? (a) S-TTL (b) AS-TTL (c) HS-TTL (d) HCMOS
- Counters » Exercise - 1112. ________ is the output frequency of the counter shown below. (a) 4 MHz (b) 20 kHz (c) 210.5 kHz (d) 800 Hz