108. In order to use a shift register as a counter, ________.
(a) the register’s serial input is the counter input and the serial output is the counter output (b) the parallel inputs provide the input signal and the output signal is taken from the serial data output (c) serial in/serial out register must be used (d) the serial output of the register is connected back to the serial input of the register
Answer
Answer : (d)
Explanation
Explanation : No answer description available for this question. Let us discuss.
5555555555 77. In order to use a shift register as a counter, ________. (a) the register's serial input is the counter input and the serial output is the counter output (b) the parallel inputs provide the input signal and the output signal is taken from the serial data output (c) a serial-in, serial-out register must be used (d) the serial output of the register is connected back to the serial input of the register
Shift Registers » Exercise - 137. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________. (a) parallel in/serial out (b) serial in/parallel out (c) serial in/serial out (d) parallel in/parallel out
Counters » Exercise - 1 6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above
Shift Registers » Exercise - 141. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output? (a) 1.67 s (b) 26.67 s (c) 26.7 ms (d) 267 ms
Shift Registers » Exercise - 170. Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output? (a) 1 (b) 7 (c) 8 (d) 9