211. –910 represented in eight-bit two’s-complement notation is ________.
(a) 11110111
(b) 11111001
(c) 11110110
(d) 01111101
212. FC48 – AB91 = ________.
(a) 5B77
(b) 5267
(c) 50B7
(d) 5077
213. 34FC + AD31 = ________.
(a) E22D
(b) E31D
(c) E21D
(d) E42D
214. In BCD addition, the value ________ is added to any invalid code group.
(a) 010101
(b) 0U812
(c) 100110
(d) 0110
215. When subtracting 6 from 9 using 2’s-complement methods, the ________ is 2’s complemented before the addition.
(a) six
(b) multiplier
(c) nine
(d) two
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51. Decimal 474 is ________ in BCD. (a) 0100 0111 0100 (b) 0100 1011 0101 (c) 0100 1001 0011 (d) 0110 1011 1001 52. The largest BCD number that can be represented with four binary bits is ________. (a) 9 (b) 10 (c) 15 (d) 16 53. The decimal equivalent of the BCD number 1010 is ________. (a) 8 (b) 10 (c) 12 (d) invalid- 101. When Karnaugh mapping, we must be sure to use the ________ number of loops. (a) maximum (b) minimum (c) median (d) Karnaugh 102. VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals. (a) objects (b) LOGIC_VECTORS (c) designs (d) arrays 103. The ________ statement evaluates the variable status. (a) IF/THEN (b) IF/THEN/ELSE (c) CASE (d) ELSIF 104. In VHDL, data can be each of the following types except ________. (a) BIT (b) BIT_VECTOR (c) STD_LOGIC (d) STD_VECTOR 105. Except for ________, STD_LOGIC may have the following values. (a) 'z' (b) 'U' (c) '?' (d) 'L' 106. After each circuit in a subsection of a VHDL program has been ________, they can be combined and the subsection can be tested. (a) designed (b) tested (c) engineered (d) produced 107. The correct output for this XOR truth table is ________. (a) (b) (c) (d) 108. In an odd-parity system, the data that will produce a parity bit = 1 is ________. (a) data = 1010011 (b) data = 1111000 (c) data = 1100000 (d) All of the above 109. Parity generation and checking is used to detect ________.…
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