113. Referring to the function table given below, taking the CLEAR, S1, and S0 inputs all HIGH ________.
(a) will inhibit the operation of the register (b) will reset the parallel registers and inhibit the serial data inputs (c) will cause the parallel data inputs to be loaded and passed to the parallel data outputs (d) will depend on what values are loaded into the parallel data inputs
Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Counters » Exercise - 1115. The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________. (a) multiplexing, 1 (b) parallel-to-serial conversion, 0 (c) demultiplexing, 0 (d) parallel-to-serial conversion, HIGH
Logic Gates » Exercise - 111. An AND gate will function as OR if : (a) All the inputs to the gates are “1” (b) All the inputs are ‘0’ (c) Either of the inputs is “1” (d) All the inputs and outputs are complemented
Shift Registers » Exercise - 168. How can parallel data be taken out of a shift register simultaneously? (a) Use the Q output of the first FF. (b) Use the Q output of the last FF. (c) Tie all of the Q outputs together. (d) Use the Q output of each FF.
Shift Registers » Exercise - 1 1. A register can also be used to provide data movements. (a) Parallel Register (b) Simple Register (c) Shift Register (d) All of the above
Shift Registers » Exercise - 1 4. This type of register accepts inputs data simultaneously and output is also coming out parallel : (a) PIPO (b) SIPO (c) PISO (d) SISO