Shift Registers » Exercise - 169. What is the difference between a shift-right register and a shift-left register? (a) There is no difference. (b) (c) (d)
Shift Registers » Exercise - 143. What is meant by parallel load of a shift register? (a) All FFs are preset with data. (b) Each FF is loaded with data, one (c) (d)
Shift Registers » Exercise - 168. How can parallel data be taken out of a shift register simultaneously? (a) Use the Q output of the first FF. (b) Use the Q output of the last FF. (c) Tie all of the Q outputs together. (d) Use the Q output of each FF.
Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000