Interrupts of 8085 Microprocessor » Exercise – 1
1. An interrupt which can be temporarily ignored by the counter is known as :
(a) Vectored interrupt
(b) Non maskable interrupt
(c) Maskable interrupt
(d) Low priority interrupt
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Interrupts of 8085 Microprocessor » Exercise - 12. An interrupt which can be temporarily ignored by the counter is known as : (a) Vectored interrupt (b) Non maskable interrupt (c) Maskable interrupt (d) Low priority interrupt- Interrupts of 8085 Microprocessor » Exercise - 1 1. An interrupt which can be temporarily ignored by the counter is known as : (a) Vectored interrupt (b) Non maskable interrupt (c) Maskable interrupt (d) Low priority interrupt 2. An interrupt which can be temporarily ignored by the counter is known as : (a) Vectored interrupt (b) Non maskable interrupt (c) Maskable interrupt (d) Low priority interrupt 3. An interrupt in which the external device supplies its address as well as the interrupt request is known as : (a) Vectored interrupt (b) Non maskable interrupt (c) Maskable interrupt (d) Designated interrupt 4. In 8085, interrupts except TRAP are disabled by (incorrect) : (a) A DI instruction (b) A system reset (c) Acknowledgement of a previous interrupt (d) None of the above 5. When a CPU is interrupted, it : (a) Stops execution of instruction (b) Acknowledges interrupt and continues (c) Acknowledges interrupt and branches to a subroutine (d) None of the above
- Counters » Exercise - 1 1. The purpose of introducing feedback loop in digital counter circuit is : (a) To improve distortion (b) To improve stability (c) Synchronise input and output pulses (d) to reduce the number of input pulses to reset the counter 2. The circuit shown below is a : (a) Mod-4 counter (b) Mod-5 counter (c) Mod-6 counter (d) Mod-7 counter 3. In this type of counter, the output of the last stage is connected to the D input of the first stage. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 4. A counter is a : (a) Sequential circuit (b) Combinational circuit (c) Both combinational and sequential circuit (d) None of above 5. A counter with 10 states : (a) Cascading asynchronous counter (b) Decade counter (c) Asynchronous ripple counter (d) Ripple counter 6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above 7. It is a sequential circuit that cycles through a sequence of states : (a) Multiplexer (b) Demultiplexer (c) Counter…
- Interrupts of 8085 Microprocessor » Exercise - 13. An interrupt in which the external device supplies its address as well as the interrupt request is known as : (a) Vectored interrupt (b) Non maskable interrupt (c) Maskable interrupt (d) Designated interrupt
- Interrupts of 8085 Microprocessor » Exercise - 15. When a CPU is interrupted, it : (a) Stops execution of instruction (b) Acknowledges interrupt and continues (c) Acknowledges interrupt and branches to a subroutine (d) None of the above