5555555555
81. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
(a) SET
(b) RESET
(c) clear
(d) invalid
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Flip-Flops » Exercise - 13. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________. (a) SET (b) RESET (c) Clear (d) Invalid- Flip-Flops » Exercise - 14. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be ________. (a) SET (b) RESET (c) Clear (d) Invalid
- 5555555555118. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in? (a) (b) (c) (d)
- 555555555550. How many flip-flops are in the 7475 IC? (a) 1 (b) 2 (c) 4 (d) 8
- 555555555578. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs? (a) active-HIGH (b) (c) (d)