5555555555
70. Edge-triggered flip-flops must have:
(a) very fast response times
(b) at least two inputs to handle rising and falling edges
(c) positive edge-detection circuits
(d) negative edge-detection circuits
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
5555555555111. Edge-triggered flip-flops must have: (a) very fast response times. (b) at least two inputs to handle rising and falling edges. (c) a pulse transition detector. (d) active-LOW inputs and complemented outputs.- 5555555555 41. Edge-triggered flip-flops must have _________. (a) very fast response times (b) at least two inputs to handle rising and falling edges (c) a positive-transition pulse generator (d) a negative-transition pulse generator
- 5555555555225. How many inputs are required for a 1-of-10 BCD decoder? (a) 4 (b) 8 (c) 10 (d) 1
- 5555555555135. How many inputs must a full-adder have? (a) 2 (b) 3 (c) 4 (d) 5
- 5555555555194. If [A] = 1011 1010, [B] = 0011 0110, and [C] = [A] • [B], what is [C 4..2] in decimal? (a) 1 (b) 2 (c) 3 (d) 4