5555555555
110. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
(a) CLK = NGT, D = 0
(b) CLK = PGT, D = 0
(c) CLOCK NGT, D = 1
(d) CLOCK PGT, D = 1[E]. CLK = NGT, D = 0, CLOCK NGT, D = 1
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant
Electronics & Communication Engineering Books
Related Posts 5555555555145. The advantage of a J-K flip-flop over an S-R FF is that ________. (a) it has fewer gates (b) it has only one output (c) it has no invalid states (d) it does not require a clock input Tags: flip, flops, flip-flop, states, clock, input, electronics, engineering
555555555589. A J-K flip-flop is in a "no change" condition when ________. (a) J = 1, K = 1 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 0, K = 0 Tags: flip, flops, flip-flop, change, electronics, engineering
555555555563. What does the triangle on the clock input of a J-K flip-flop mean? (a) level enabled (b) edg (c) (d) Tags: flip, flops, clock, input, flip-flop, electronics, engineering
555555555572. What is the difference between the enable input of the 7475 and the clock input of the 7474? (a) The 7475 is edge-triggered. (b) (c) (d) Tags: input, flip, flops, clock, electronics, engineering
5555555555117. What is one disadvantage of an S-R flip-flop? (a) It has no enable input. (b) It has an invalid state. (c) It has no clock input. (d) It has only a single output. Tags: input, flip, flops, flip-flop, state, clock, electronics, engineering