6. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state.
(a) Ring Counter
(b) Johnson Counter
(c) Straight Counter
(d) None of the aboveSubject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant Electronics & Communication Engineering Books
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Counters » Exercise - 1 3. In this type of counter, the output of the last stage is connected to the D input of the first stage. (a) Ring Counter (b) Johnson Counter (c) Straight Counter (d) None of the above- Counters » Exercise - 1109. The circuit shown below is a ________. (a) Johnson counter (b) ring counter (c) decade counter (d) BCD counter
- Counters » Exercise - 121. Which of the following is an invalid state in an 8421 BCD counter? (a) 0011 (b) 1001 (c) 1000 (d) 1100
- Counters » Exercise - 1105. A BCD counter has ________ states. (a) 8 (b) 9 (c) 10 (d) 11
- Counters » Exercise - 1111. ________ is the modulus of the counter shown below. (a) 200 (b) 19 (c) 0.005 (d) 5000