5555555555
174. Using 4-bit adders to create a 1See Section 6-bit adder:
(a) requires 16 adders.
(b) requires 4 adders.
(c) requires the carry-out of the less significant adder to be connected to the carry-in of the next significant adder.
(d) requires 4 adders and the connection of the carry out of the less significant adder to the carry-in of the next significant adder.
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
555555555585. A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________. (a) 01100 (b) 10101 (c) 11000 (d) 00011- 5555555555201. The carry-out of a full adder is ________. (a) (b) (c) (d)
- 5555555555195. If B[7..0] = 10100101, what is the value of B[6..2]? (a) 10100 (b) 01001 (c) 10010 (d) 00101
- 5555555555121. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is: (a) the same as if the carry-in is tied LOW since the least significant carry-in is ignored. (b) that carry-out will always be HIGH. (c) a one will be added to the final result. (d) the carry-out is ignored.
- Arithmetic Circuits » Exercise - 13. A half adder can be used only for adding : (a) 1s (b) 2s (c) 4s (d) 8s