11. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:
(a) sample and hold the output of the binary counter during the conversion process
(b) stabilize the comparator’s threshold voltage during the conversion process
(c) stabilize the input analog signal during the conversion process
(d) sample and hold the D/A converter staircase waveform during the conversion process
12. The primary disadvantage of the flash analog-to digital converter (ADC) is that:
(a) it requires the input voltage to be applied to the inputs simultaneously
(b) a long conversion time is required
(c) a large number of output lines is required to simultaneously decode the input voltage
(d) a large number of comparators is required to represent a reasonable sized binary number
13. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter?
(a) It only uses two different resistor values.
(b) It has fewer parts for the same number of inputs.
(c) Its operation is much easier to analyze.
(d) The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot.
14. A binary-weighted digital-to-analog converter has a feedback resistor, Rf, of 12 k. If 50 A of current is through the resistor, the voltage out of the circuit is:
(a) 0.6 V
(b) –0.6 V
(c) 0.1 V
(d) –0.1 V
15. The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the:
(a) quantization
(b) accuracy
(c) resolution
(d) monotonicity
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