Architecture and Organization of 8085 Microprocessor » Exercise – 1
1. The flow and timing of data to and from the mp is regulated by :
(a) Control pins
(b) Data pins
(c) Address pins
(d) Power pins
2. A mp with 12 address lines is capable of addressing :
(a) 1024 locations
(b) 2048 locations
(c) 4096 locations
(d) 64K locations
3. The bus which is used to transfer data from main memory to the peripheral devices :
(a) Data bus
(b) Input bus
(c) DMA bus
(d) Output bus
4. Two operands can be checked for equality using :
(a) OR operation
(b) AND operation
(c) EXOR operation
(d) None of the above
5. Which of the following signals are used when a peripheral device request the mp to have a DMA operation :
(a) IO/M
(b) READY
(c) HOLD and HLDA
(d) Read and write
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