5555555555
82. How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?
(a) 2
(b) 4
(c) 8
(d) 16
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
5555555555100. How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system? (a) 2 (b) 4 (c) 8 (d) 16- 555555555585. How many address lines would be required for a 2K × 4 memory chip? (a) 8 (b) 10 (c) 11 (d) 12
- 555555555537. How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM? (a) 8 (b) 10 (c) 14 (d) 16
- 5555555555152. The checksum method is used to test ________. (a) ROM (b) EEPROM (c) FPLA (d) RAM
- 555555555531. ________ is an example of read/write memory. (a) PROM (b) EEPROM (c) RAM (d) MROM