5555555555
71. What must be done to interface CMOS to TTL?
(a) A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.
(b) As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
(c) A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates.
(d) The two series cannot be interfaced without the use of special interface buffers designed for that purpose, such as the open-collector buffers.
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
555555555570. What must be done to interface TTL to CMOS? (a) A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL. (b) As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the TTL is limited to five CMOS gates. (c) A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates. (d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node.- 5555555555127. The nominal value of the dc supply voltage for TTL and CMOS is ________. (a) +3 V (b) +5 V (c) +9 V (d) +12 V
- Logic Gates » Exercise - 130. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates ? (a) OR gates only (b) OR gates and NOT gates (c) AND gates and NOT gates (d) AND gates, OR gates, and NOT gates
- 555555555564. What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)? (a) 5 (b) 10 (c) 50 (d) 100
- 5555555555104. The HIGH logic level for a standard TTL output must be at least ________. (a) 2.4 V (b) 2 V (c) 0.8 V (d) 5 V