5555555555
58. ________ output levels would not be a valid LOW for a TTL gate.
(a) 0.2 V
(b) 0.3 V
(c) 0.5 V
(d) All of the above.
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
555555555597. Fan-out for a typical TTL gate is ________. (a) 100 (b) 54 (c) 10 (d) 4- 555555555529. Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? (a) Yes (b) No Answ (c) (d)
- 555555555547. What is the range of invalid TTL output voltage? (a) 0.0–0.4 V (b) 0.4–2.4 V (c) 2.4–5.0 V (d) 0.0–5.0 V
- 5555555555122. Which is not an output state for tristate logic? (a) HIGH (b) LOW (c) High-Z (d) Low-Z
- 555555555528. How many 74LSTTL logic gates can be driven from a 74TTL gate? (a) 10 (b) 20 (c) 200 (d) 400