Frequency Domain Analysis » Exercise – 1
23. The phase margin of a system is 0˚. It represents a :
(a) stable system
(b) unstable system
(c) conditionally stable system
(d) marginally stable systemSubject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant Electronics & Communication Engineering Books
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