Counters – Exercise – 3

111. ________ is the modulus of the counter shown below.

(a) 200
(b) 19
(c) 0.005
(d) 5000

112. ________ is the output frequency of the counter shown below.

(a) 4 MHz
(b) 20 kHz
(c) 210.5 kHz
(d) 800 Hz

113. Referring to the function table given below, taking the CLEAR, S1, and S0 inputs all HIGH ________.

(a) will inhibit the operation of the register
(b) will reset the parallel registers and inhibit the serial data inputs
(c) will cause the parallel data inputs to be loaded and passed to the parallel data outputs
(d) will depend on what values are loaded into the parallel data inputs

114. Modulus refers to ________.

(a) a method used to fabricate decade counter units
(b) the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
(c) an input on a counter that is used to set the counter state, such as UP/DOWN
(d) the maximum number of states in a counter sequence

115. The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.

(a) multiplexing, 1
(b) parallel-to-serial conversion, 0
(c) demultiplexing, 0
(d) parallel-to-serial conversion, HIGH

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