16. Nota
17. In VHDL, the mode of a port does not define:
(a) an input.
(b) an output.
(c) both an input and an output.
(d) the TYPE of the bit.
18. How are the statements between BEGIN and END not evaluated in VHDL?
(a) Constantly
(b) Simultaneously
(c) Concurrently
(d) Sequentially
19. Determine the values of A, B, C, and D that make the sum term equal to zero.
(a) A = 1, B = 0, C = 0, D = 0
(b) A = 1, B = 0, C = 1, D = 0
(c) A = 0, B = 1, C = 0, D = 0
(d) A = 1, B = 0, C = 1, D = 1
20. Derive the Boolean expression for the logic circuit shown below:
(a)
(b)
(c)
(d)
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