Time Domain Analysis » Exercise – 1
22. The steady – state error of a first – order system to a ramp input is equal to :
(a) the time constant of the system
(b) zero
(c) infinity
(d) none of theseSubject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant Electronics & Communication Engineering Books
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