12. With reference to JFET configuration, match the following
(P) Common Source Configuration (1) No phase shift between input & output
(Q) Common Drain Configuration (2) High input impedance & low output impedance
(R) Common Gate Configuration (3) Source follower Configuration
(a) P-1, Q-2, R-3
(b) P-2, Q-3, R-1
(c) P-2, Q-1, R-3
(d) P-3, Q-1, R-2Subject Name : Electronics Engineering Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant Electronics & Communication Engineering Books
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