Instruction Timing Diagram of 8085 Microprocessor » Exercise – 1
2. The no. of minimum clock cycle in a m/c cycle for 8085 are :
(a) 1
(b) 2
(c) 3
(d) 5
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books |
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Instruction Timing Diagram of 8085 Microprocessor » Exercise - 1 1. An instruction cycle is made up of : (a) One or more execute cycles (b) One or more fetch cycles (c) One opcode and one fetch cycle (d) None of the above- Instruction Timing Diagram of 8085 Microprocessor » Exercise - 14. Which of the following cycles are required to fetch and execute information : (a) Clock cycles (b) T cycles (c) Instruction cycle (d) Memory cycle
- 5555555555179. Which timing diagram shown below is correct for an inverter? (a) a (b) b (c) c (d) d
- Instruction Timing Diagram of 8085 Microprocessor » Exercise - 13. In a 8 bit mp, the fetch cycle required to fetch a 8 bit instruction will be : (a) 1 (b) 2 (c) 3 (d) Depends on the computer design
- Instruction Timing Diagram of 8085 Microprocessor » Exercise - 110. CMP M has : (a) 1 machine cycle (b) 2 machine cycles (c) 3 machine cycles (d) 4 machine cycles