5555555555 74. When the output of a tri-state shift register is disabled, the output level is placed in a: (a) float state (b) LOW state (c) high impedance state (d) float state and a high impedance state
Shift Registers » Exercise - 157. What are the three output conditions of a three-state buffer? (a) HIGH, LOW, float (b) 1, 0, float (c) both of the above (d) neither of the above
Shift Registers » Exercise - 128. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. (a) 10111000 (b) 10110111 (c) 11110000 (d) 11111100