156. The memory operation that stores data into a memory location after entering a new address is called ________.
(a) a read cycle
(b) a write cycle
(c) a refresh cycle
(d) chip select
157. The memory operation that presents data on the memory outputs after entering a new address is called ________.
(a) a read cycle
(b) a write cycle
(c) a refresh cycle
(d) a chip select
158. Read-only memory is memory ________.
(a) that has unlimited storage capacity
(b) whose data can never be altered by the user
(c) that must be refreshed periodically or it will lose storage
(d) that maintains storage as long as power is applied
159. Dynamic memory is memory ________.
(a) that will maintain storage even if power is removed
(b) whose data can never be altered
(c) that must be refreshed periodically or it will lose storage
(d) that maintains storage as long as power is applied
160. The address space of a RAM memory can be expanded using a decoder and additional memory ICs. The output of the decoder should be connected to which input line of the memory?
(a) The most significant address inputs
(b) The most significant data inputs
(c) The read/write line
(d) The chip enable
Related Posts
51. The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit? (a) The Q0, Q2, and Q3 output lines are open; the chip is defective. (b) The Q1 line appears to be shorted to Vcc; replace the chip. (c) The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH. (d) The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced. 52. Which of the following faults will the checkerboard pattern test for in RAM? (a) Short between adjacent cells (b) Ability to store both 0s and 1s (c) Dynamically introduced between…- Home » Electronics Engineering » Microprocessors and Microcontrollers » IO and Memory Interfacing
- Home » Electronics Engineering » Digital Electronics » Memory Devices
- Home » Computer Science » Data Communications and Computer Networks » Modem
- Home » Computer Science » Data Communications and Computer Networks » X.25 Protocol