146. In DRAM operations, it is assumed that R/W is in its ________ state during a ________ operation.
(a) HIGH, read
(b) Hi-Z, write
(c) HIGH, write
(d) Hi-Z, read
147. Flash memories are so called because of the rapid ________ times.
(a) read and write
(b) format and erase
(c) erase and read
(d) erase and write
148. Because of their nonvolatility, high speed, low power requirements, and lack of moving parts, ________ have become feasible alternatives to magnetic disk storage.
(a) CD-ROMs
(b) flash memory modules
(c) ROMs
(d) EPROMs
149. When a computer is executing a program of instructions, the CPU will ________ memory locations as dictated by the program instructions.
(a) format
(b) scan
(c) store data into
(d) verify
150. When more than one IC is used to provide all the addressable locations in a memory, a technique called ________ is used to identify which IC is being accessed.
(a) address decoding
(b) memory refresh
(c) data encoding
(d) memory paging
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51. The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit? (a) The Q0, Q2, and Q3 output lines are open; the chip is defective. (b) The Q1 line appears to be shorted to Vcc; replace the chip. (c) The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH. (d) The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced. 52. Which of the following faults will the checkerboard pattern test for in RAM? (a) Short between adjacent cells (b) Ability to store both 0s and 1s (c) Dynamically introduced between…- 151. Because 4096 = 212, a 4K × 1 RAM requires ________ address bits to access all locations. (a) 4096 (b) 10 (c) 12 (d) 1024 152. The checksum method is used to test ________. (a) ROM (b) EEPROM (c) FPLA (d) RAM 153. A FIFO ________. (a) allows data to be clocked in and out at different clock rates (b) outputs the data in the same order that it was input (c) can be used to smooth out bursts of data into a continuous stream (d) All of the above 154. The major advantage of dynamic RAM over static RAM is ________. (a) cost (b) speed (c) storage density (d) cost and storage density 155. Dynamic RAMs store information by using ________. (a) magnetism (b) flip-flops (c) latches (d) capacitors 156. The memory operation that stores data into a memory location after entering a new address is called ________. (a) a read cycle (b) a write cycle (c) a refresh cycle (d) chip select 157. The memory operation that presents data on the memory outputs after entering a new address is called ________. (a) a read cycle (b) a write cycle (c) a refresh cycle (d) a chip select…
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