Counters – Exercise – 1

46. The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem?

(a) The data output line may be grounded.
(b) One of the clock input lines may be open.
(c) One of the interconnect lines between two stages may have a solder bridge to ground.
(d) One of the flip-flops may have a solder bridge between its input and Vcc.

47. In an HDL ring counter, many invalid states are included in the programming by:

(a) using a case statement.
(b) using an elsif statement.
(c) including them under others.
(d) the ser_in line.

48. For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?

(a) By using a counter
(b) By using an active clock
(c) By using an immediate reload
(d) By using edge trapping

49. In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

(a) A trigger edge has occurred and we must load the counter.
(b) The counter is zero and we need to keep it at zero.
(c) The shift register is reset.
(d) The counter is not zero and we need to count down by one.

50. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

(a) Five flip-flops, three AND gates
(b) Seven flip-flops, five AND gates
(c) Four flip-flops, ten AND gates
(d) Six flip-flops, four AND gates

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