Combinational Circuits – Exercise – 3

121. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is:

(a) the same as if the carry-in is tied LOW since the least significant carry-in is ignored.
(b) that carry-out will always be HIGH.
(c) a one will be added to the final result.
(d) the carry-out is ignored.

Answer
Answer : (c)
Explanation
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122. What is the first thing you will need if you are going to use a macrofunction?

(a) A complicated design project
(b) An experienced design engineer
(c) Good documentation
(d) Experience in HDL

Answer
Answer : (c)
Explanation
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123. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?

(a) to decrease the cost
(b) to make it smaller
(c) to slow down the circuit
(d) to speed up the circuit

Answer
Answer : (d)
Explanation
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124. The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:

(a) ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros
(b) add 0110 to both code groups to validate the carry from the lowest order code group
(c) disregard the carry and add 0110 to the lowest order code group
(d) add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros

Answer
Answer : (d)
Explanation
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125. Could the sum output of a full-adder be used as a two-bit parity generator?

(a) Yes
(b)
(c)
(d)

Answer
Answer : (a)
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