56. What is the indication of a short to ground in the output of a driving gate?
(a) Only the output of the defective gate is affected.
(b) There is a signal loss to all load gates.
(c) The node may be stuck in either the HIGH or the LOW state.
(d) The affected node will be stuck in the HIGH state.
57. Nota
58. What will a design engineer do after he/she is satisfied that the design will work?
(a) Put it in a flow chart
(b) Program a chip and test it
(c) Give the design to a technician to verify the design
(d) Perform a vector test
59. In HDL, LITERALS is/are:
(a) digital systems.
(b) scalars.
(c) binary coded decimals.
(d) a numbering system.
60. An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?
(a) Current tracer
(b) Logic probe
(c) Oscilloscope
(d) Logic analyzer
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Logic Gates » Exercise - 2 51. Which type of gate can be used to add two bits? (a) Ex-OR (b) Ex-NOR (c) Ex-NAND (d) NOR 52. Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function. (a) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B. (b) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B. (c) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B. (d) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B. 53. Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted. (a) positive, negative, byte (b) odd, even, bit (c) upper, lower, digit (d) on, off, decimal 54. The Ex-NOR is sometimes called…- 101. How many inputs are on the logic gates of a 74HC21 IC? (a) 1 (b) 2 (c) 3 (d) 4 102. What are the pin numbers of the outputs of the gates in a 7432 IC? (a) 3, 6, 10, and 13 (b) 1, 4, 10, and 13 (c) 3, 6, 8, and 11 (d) 1, 4, 8, and 11 103. How many AND gates are found in a 7411 IC? (a) 1 (b) 2 (c) 3 (d) 4 104. Which of the following equations would accurately describe a four-input OR gate when A = 1, B = 1, C = 0, and D = 0? (a) 1 + 1 + 0 + 0 = 01 (b) 1 + 1 + 0 + 0 = 1 (c) 1 + 1 + 0 + 0 = 0 (d) 1 + 1 + 0 + 0 = 00 105. Which of the following logical operations is represented by the + sign in Boolean algebra? (a) inversion (b) AND (c) OR (d) complementation 106. The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is HIGH is a(n): (a) OR gate (b)…
- 51. Which of the following logic families has the shortest propagation delay? (a) S-TTL (b) AS-TTL (c) HS-TTL (d) HCMOS 52. Which of the following logic families has the highest maximum clock frequency? (a) S-TTL (b) AS-TTL (c) HS-TTL (d) HCMOS 53. Which of the following will not normally be found on a data sheet? (a) Minimum HIGH level output voltage (b) Maximum LOW level output voltage (c) Minimum LOW level output voltage (d) Maximum HIGH level input current 54. Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have: (a) a greater current/voltage capability than an ordinary logic circuit. (b) greater input current/voltage capability than an ordinary logic circuit. (c) a smaller output current/voltage capability than an ordinary logic. (d) greater input and output current/voltage capability than an ordinary logic circuit. 55. Why is the fan-out of CMOS gates frequency dependent? (a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate. (b) When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the…
- 151. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 152. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 153. The symbol shown represents a(n) ________. (a) AND gate (b) OR gate (c) NAND gate (d) NOR gate 154. The symbol shown represents ________. (a) AND-OR logic (b) AOI logic (c) XOR gate (d) XNOR gate 155. The expression can be directly implemented using only ________. (a) an XOR gate (b) an XNOR gate (c) an AOI circuit (d) three 2-input NAND gates 156. Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. (a) 3 (b) 4 (c) 5 (d) 6 157. A gate can drive a number of load gate inputs up to its specified ________. (a) supply voltage (b) noise margin (c) fan-in (d) fan-out 158. If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. (a) OR gate (b) AND gate…
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