Flip Flops – 15

Flip-Flops » Exercise – 1

15. In a positive edge triggered JK flip flop, a low J and low K produces ?

(a) high state
(b) low state
(c) toggle state
(d) no change

Answer
Answer : (d)

Explanation
Explanation : No answer description available for this question. Let us discuss.
General Knowledge Books

Related Posts

  • Flip Flops - 22Flip-Flops » Exercise - 122. Which one flip flop has an invalid output state. (a) JK flip flop (b) T flip flop (c) SR flip flop (d) D flip flop
    Tags: flip, flop, flops, flip-flops, exercise, state, jk, electronics, engineering
  • Logic Families - 48555555555548. From the following specifications determine the fan-out for the logic family. (a) HIGH state is 16, LOW state is 8 (b) HIGH state is 8, LOW state is 16 (c) HIGH state is 4, LOW state is 8 (d) HIGH state is 8, LOW state is 4
    Tags: state, high, low, electronics, engineering
  • Flip Flops - 61555555555561. On a master-slave flip-flop, when is the master enabled? (a) when the gate is LOW (b) when the gate is HIGH (c) both of the above (d) neither of the above
    Tags: flip, flops, low, high, electronics, engineering
  • Flip Flops - 50555555555550. How many flip-flops are in the 7475 IC? (a) 1 (b) 2 (c) 4 (d) 8
    Tags: flip, flops, flip-flops, electronics, engineering
  • Flip Flops - 49555555555549. How is a J-K flip-flop made to toggle? (a) J = 0, K = 0 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 1, K = 1
    Tags: flip, flops, toggle, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here