1. A latch has _____ stable states.
2. An S-R latch can be implemented by using _______ gates.
(a) AND, OR
(b) NAND, NOR
(c) NAND, XOR
(d) NOT, XOR
3. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
4. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be ________.
5. Gated S-R latch is a combination of which latch and gate ?
(a) J-K latch and NOR gate
(b) S-R latch and NAND gate
(c) S-R latch and NOR gate
(d) J-K latch and NAND gate
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