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Architecture & Organization of 8085 Microprocessor – 1 – 1

1. The flow and timing of data to and from the mp is  regulated by :

(a) Control pins
(b) Data pins
(c) Address pins
(d) Power pins

ANSWER

EXPLANATION

2. A mp with 12 address lines is capable of addressing :

(a) 1024 locations
(b) 2048 locations
(c) 4096 locations
(d) 64K locations

ANSWER

EXPLANATION

3. The bus which is used to transfer data from main memory to the peripheral devices :

(a) Data bus
(b) Input bus
(c) DMA bus
(d) Output bus

ANSWER

EXPLANATION

4. Two operands can be checked for equality using :

(a) OR operation
(b) AND operation
(c) EXOR operation
(d) None of the above

ANSWER

EXPLANATION

5. Which of the following signals are used when a peripheral device request the mp to have a DMA operation :

(a) IO/M
(b) READY
(c) HOLD and HLDA
(d) Read and write

ANSWER

EXPLANATION

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